1. Field of the Invention
This invention relates generally to integrated circuits and, in particular, to input/output circuits of integrated circuits.
2. Description of the Related Art
Input/output ("I/O") circuits are used to input electronic signals to and output electronic signals from integrated circuits. A typical integrated circuit ("IC") includes an integral I/O circuit for each of its externally accessible I/O pins. An I/O circuit usually includes a driver circuit which receives signals from the IC and outputs them to the I/O pin. The driver circuit may also herein be referred to as the output driver. It also generally includes an input buffer which receives signals from the I/O pin and inputs them to the IC. A typical I/O circuit also includes an enable circuit which can place the driver circuit in either a high impedance state in which signals can be input to the IC via the I/O pin, or in an output enabled state in which signals can be output from the IC via the I/O pin.
I/O circuits transfer signals to and from integrated circuit devices in a variety of types of electronic systems. For instance, I/O circuits may be used to interconnect integrated circuits to a shared system bus so that multiple ICs connected to the bus can communicate with each other. In many electronic systems all of the integrated circuits connected to a system bus operate at the same supply voltage level. However, as the dimensions of the circuits in ICs have decreased, the supply voltages employed by ICs also have decreased. As a result, there has been a proliferation of mixed signal systems in which some ICs connected to a system bus operate at a higher supply voltage (e.g., 5-volts), and other ICs connected to the same system bus operate at a lower supply voltage (e.g., 3.3-volts).
A problem with mixed signal systems has been the occurrence of leakage currents, over the system bus, from an IC operating at a higher supply voltage to an IC operating at a lower supply voltage. For instance, an IC operating with a 3.3 volt supply may experience an overvoltage when an IC connected to the same bus as the 3.3 volt device drives a 5 volt signal onto the bus. An IC may experience an overvoltage, for example, when the voltage on one of its I/O pins is greater than the IC's internal supply voltage. As used herein, an IC's internal voltage includes both core and peripheral supply voltages, which may have the same or different values. Thus, leakage current may result when an output level high signal is imparted from one IC onto an I/O pin of another IC operating at a lower supply voltage.
The illustrative drawing of FIG. 1 shows a pull-up/pull-down driver circuit which will be used to explain such leakage currents. The driver circuit includes a pull-up driver 110 and a pull-down driver 115. In this example, pull-up driver 110 is a p-channel (PMOS) transistor, and pull-down driver 115 is an n-channel (NMOS) transistor. Pull-up driver 110 is coupled between a supply voltage 117 and a pin (or pad) 120. Pin 120 is referred to as an I/O pin as it may be used for input or output, or both. Pull-down driver 115 is coupled between pin 120 and a supply voltage 122. Supply 117 is typically V.sub.DD or V.sub.CC, each of which may be referred to as the internal supply voltage or drive voltage, and supply 122 is typically V.sub.SS, which is typically at a low voltage, such as ground potential.
In operation, the output buffer will generate a logic high, logic low, or be tristated (i.e., high impedance state) depending on the logic signals at PU and PD. PU is provided to a gate of pull-up driver 110, and PD is provided to a gate of pull-down driver 115. When PU is a low and PD is a low, the pull-up drive 110 is ON and the pull-down driver 115 is OFF, and the pin will be driven high (to the level of V.sub.CC). When PU is high and PD is high, the pull-up driver 110 is OFF and the pull-down driver 115 is ON, and the pin will be driven low (to the level of V.sub.SS). When PU is high and PD is low, both the pull-up driver 110 and the pull-down driver 115 are OFF, and the pin 120 will be tristated. Pin 120 is typically also coupled to an input buffer (not shown) for the inputting of logical signals into the integrated circuit and the core. Pin 120 may be used as an input when the output buffer is placed in tristate, or may also be used to feed back signals from the output buffer into the integrated circuit.
However, the driver circuit shown in FIG. 1 is not tolerant to high voltages, and may not be useful in the case where input voltages are imparted by an integrated circuit having a supply voltage above a level of the first supply voltage 117. For example, when the output buffer is tristated, signals are input to the input buffer (not shown) via pin 120. If first supply 117 is 3.3 volts, then when interfacing a 5-volt integrated circuit, pin 120 may potentially be at 5 volts or above. A 5-volt input would represent a logic high input. This voltage may even go above 5 volts during transitions due to overshoots. This poses potential problems.
An I1 current sneak path (or leakage path) may occur when the VPIN (the voltage level at the pin) goes above 3.3 volts+.vertline.VTP110.vertline.. VTP110 is the threshold voltage of pull-up driver 110. Furthermore, in an embodiment, pull-up driver 110 is a PMOS transistor and formed in an n-well on a p-type substrate. In that case, there may be a parasitic diode 130 between pin 120 and first supply 117. Parasitic diode 130 represents the diode between the p-diffusion used to form the drain and the n-well region, which is connected to the first supply voltage 117. Therefore, an I2 current sneak path will also occur when the VPIN goes above 3.3 volts+Vdiode. Vdiode is the turn-on or forward voltage (VF) of the diode.
Leakage current paths I1 and I2 represent a DC (direct current) path which can cause the first supply (V.sub.CC) to rise. If V.sub.CC rises above maximum allowable levels and remains at those levels for longer than an acceptable time, the device, as well as other devices connected to V.sub.CC, may have oxide reliability issues. One solution to the problem of leakage currents in mixed signal systems is to provide voltage overshoot protection that blocks the flow of leakage current in overshoot situations.
Some examples of solutions to current leakage problems resulting from voltage overshoot on I/O pins are proposed in the following patents: U.S. Pat. No. 5,151,619, entitled, "CMOS Off Chip Driver Circuit", issued to Austin, et al.; U.S. Pat. No. 5,450,025, entitled, "Tristate Buffer For Interfacing to a Bus Subject to Overvoltage Conditions", issued to Shay; U.S. Pat. No. 5,396,128, entitled, "Output Circuit For Interfacing Integrated Circuits Having Different Power Supply Potentials", issued to Dunning, et al.; U.S. Pat. No. 5,467,031, entitled, "3.3 Volt CMOS Tri-State Driver Circuit Capable of Driving Common 5 Volt Line", issued to Nguyen, et al.; and U.S. Pat. No. 5,546,019, entitled, "CMOS I/O Circuit With 3.3 Volt Output And Tolerance of 5 Volt Input", issued to Liao. Another example of an overvoltage-tolerant I/O circuit is disclosed in U.S. patent application Ser. No. 08/863,886, filed May 27, 1997, and entitled Overvoltage-Tolerant Interface For Integrated Circuit, which is assigned to the assignee of the present invention and is incorporated herein by reference.
Thus, in a mixed signal systems it is desirable to have I/O pins that tolerate voltages that are higher than the internal supply voltage. For example, if the internal supply is at 3.3 volts, it is desirable to have I/O pins that tolerate 5 volt inputs. In other words, it is desirable to have I/O pins that accept a 5 volt input while also avoiding leakage currents.
Some applications may, on the other hand, require sinking a certain amount of current when the I/O pin voltage exceeds some limit. For example, in Peripheral Component Interconnect (PCI) compliant systems, an I/O pin may be required to provide a clamping current greater than 20 milliamperes (mA) when the I/O pin voltage is 1 volt or more above the internal supply voltage. A purpose of this requirement, for example, is to sink current in order to quickly dissipate ringing voltage overshoot excursions on an I/O pin.
From a practical standpoint, it is desirable for ICs to be built to be useable in either a mixed signal system or a PCI system or in both simultaneously, for example. Unfortunately, as explained above, the performance requirements of these different systems often may be at odds with each other. Specifically, an I/O circuit in a typical mixed signal system blocks the current flow in overvoltage situations. In contrast, an I/O circuit in a PCI compliant system must conduct (or sink) current from an I/O pin in overvoltage situations.
An earlier solution to these conflicting requirements was to add individual internal diodes with anodes connected to the I/O pins and with cathodes connected to an internal Vtt rail. This solution is described in, "Low-Voltage FPGAs Allow 3.3-V/5-V System Design", Electronic Design, Aug. 18, 1997, by Peter Alfke; and Application Note, XAPP 088, Nov. 12, 1997 (Version 1.0), by Xilinx, Inc, San Jose, Calif. This internal Vtt rail is internally connected to multiple I/O pins. For PCI compliance, this Vtt rail is connected externally to the appropriate supply voltage, 5 volts or 3.3 volts, for example. For mixed signal tolerant systems, the Vtt rail is left unconnected or floating.
There are shortcomings with this solution. Since multiple I/O pins all are internally connected to the Vtt rail, eight in the reference documents identified above, these I/O pins cannot be configured individually to operate in PCI compatible mode or a mixed signal tolerant mode. Rather, they are configured collectively, or as a group. Moreover, the actual process of configuring the multiple I/O pins involves externally connecting the Vtt rail for PCI system operation or leaving it unconnected for mixed signal system operation. Connecting the Vtt rail or leaving it unconnected typically involves printed circuit board (PCB) level design decisions which may be difficult to change if there is a change in the plans for I/O pin usage later in an overall system design process.
FIG. 2 is a schematic diagram of another earlier system for dealing with the dual requirements of overvoltage tolerance and clamping voltages. The I/O circuit of FIG. 2 is described in more detail in U.S. patent application Ser. No. 09/057,361, filed Apr. 8, 1998, and entitled Integrated Circuit With Both Clamp Protection And High Impedance Protection From Input Overshoot, which is assigned to the assignee of the present invention and is incorporated herein by reference.
In FIG. 2, depending on the state of transistor 201, which is a large p-channel (PMOS) transistor, I/O circuit 200 may be overvoltage tolerant or clamp the voltage at I/O pin 210. When transistor 201 is ON, the well of pull-up transistor 206 is shorted to the internal supply voltage V.sub.CC and the voltage at I/O pin 210 is clamped so as not to exceed V.sub.CC +.vertline.VTP206.vertline.. .vertline.VTP206.vertline. is the absolute value of the threshold voltage of pull-up transistor 206. On the other hand, when the transistor 201 is OFF, the I/O circuit 200 is overvoltage tolerant and the voltage at the well of pull-up transistor 206 is the higher of the internal supply voltage V.sub.CC or the I/O pin voltage.
If I/O circuit 200 is to be overvoltage tolerant, then lever shifter (LS) 202 is caused to produce a high output. The high output of LS 202 causes transistor 201 to be OFF. When transistor 201 is OFF, the well bias circuitry 215 biases the well of the pull-up transistor 206 to the higher of the internal supply voltage V.sub.CC or the I/O pin voltage. Consequently, when the I/O pin voltage is higher than the internal supply voltage V.sub.CC, then the well of the pull-up transistor 206 is biased to the I/O pin voltage. Thus, the well bias circuitry 215 makes I/O circuit 200 overvoltage tolerant.
If it is desired to clamp the I/O pin voltage, then LS 202 is caused to produce a low output. The low output of LS 202 causes transistor 201 to turn ON. This in turn causes the well of the pull-up transistor 206 to be shorted to the internal supply voltage V.sub.CC. Thus, transistor 206 acts as a well clamping transistor. The clamping current for clamping the well of the pull-up transistor 206 to the internal supply voltage V.sub.CC is provided by the well of the pull-up transistor 206 and diode 290. The clamping current is then sunk via transistor 201 and diode 290 at the internal voltage supply V.sub.CC.
Although the I/O circuit 200 provides both overvoltage tolerance and voltage clamping, it has some features that may not be desirable in some circumstances. First, both transistor 201 and LS 202 are rather large. Second, forward biasing of diode 290 requires greater latch-up precaution than would otherwise be needed. The latch-up precautions include use of guard rings and increasing the spacing of transistors in the I/O circuit. These result in an increase in the size of the I/O circuit 200 and the IC of which it is a part. Third, the clamping current is sunk to the internal voltage supply V.sub.CC. If the internal voltage supply V.sub.CC is weak, then when several I/O circuits sink their clamping currents into the internal voltage supply V.sub.CC, the internal voltage supply V.sub.CC may drift to a higher voltage. If the internal supply voltage V.sub.CC rises above maximum allowable levels and remains at those levels for longer than an acceptable time, then the internal transistors of the IC may be stressed more and the IC may have oxide reliability issues.
As a result, there has been a need for integrated circuits with I/O circuitry that meets the aforementioned dual requirements while avoiding the above-mentioned shortcomings of the earlier systems. The present invention meets this need.